Improvements to Technology Mapping for LUT-Based FPGAs
نویسندگان
چکیده
منابع مشابه
Power-aware technology mapping for LUT-based FPGAs
We present a new power-aware technology mapping technique for LUT-based FPGAs which aims to keep nets with high switching activity out of the FPGA routing network and takes an activity-conscious approach to logic replication. Logic replication is known to be crucial for optimizing depth in technology mapping; an important contribution of our work is to recognize the effect of logic replication ...
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1;2 A major drawback of the previous algorithms that perform decomposition and covering for LUT-based FPGA technology mapping is the lack of a fast, and reasonably accurate evaluation scheme for the decomposition phase. In this paper, we will show how a fast covering algorithm can be used as an evaluation engine for the decomposition phase. We show that decomposition has a signi cant impact on ...
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Flowmap ((1]) was the rst delay-optimal algorithm for the technology mapping of LUT-based FPGAs. However, even though this algorithm is polynomial, rapid prototyping using FPGAs requires faster solutions. This paper provides an eecient parallelization of flowmap that minimizes locking on shared memory architectures. The innuence of scheduling strategies and technology-speciic parameters on spee...
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The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing performance-driven technology mapping algorithms for Lookup-table (LUT) based FPGA designs are based on unit delay model. In this paper we present an efficient algorithm which finds an optimal technology mapping solution with minimum delay under arbitrary net delay models for LUTbased...
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A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. The whole chip is configured as a group of one-dimensional iterative logic arrays of cells. We assume ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2007
ISSN: 0278-0070
DOI: 10.1109/tcad.2006.887925